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preliminary rev. 0.25 5/07 copyright ? 2007 by silicon laboratories si5325 this information applies to a product under dev elopment. its characteristics and specifications are s ubject to change without n otice. si5325 p-p rogrammable p recision c lock m ultiplier description the si5325 is a low jitter, precision clock multiplier for applications requiring clock mu ltiplication without jitter attenuation. the si5325 accepts dual clock inputs ranging from 10 to 710 mhz and generates two clock outputs ranging from 10 to 945 mhz and select frequencies to 1.4 ghz. the two outputs are divided down separately from a common source. the device provides virtually any frequency translation combination across this operating range. the si5325 input clock frequency and clock multiplication ratio are programmable through an i 2 c or spi interface. the si5325 is based on silicon laboratories' 3rd-generation dspll ? technology, which provides any-rate frequency synthesis in a highly integrat ed pll solution that eliminates the need for external vcxo and loop filter components. the dspll loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. operating from a single 1.8, 2. 5, or 3.3 v supply, the si5325 is ideal for providing clock multiplication in high performance timing applications . applications sonet/sdh oc-48/oc-192 line cards gbe/10gbe, 1/2/4/ 8/10gfc line cards itu g.709 and custom fec line cards optical modules wireless basestations data converter clocking xdsl sonet/sdh + pdh clock synthesis test and measurement features generates any frequency from 10 to 945 mhz and select frequencies to 1.4 ghz from an input frequency of 10 to 710 mhz low jitter clock outputs w/jitter generation as low as 0.6 ps rms (30 khz?1.3 mhz) integrated loop filter with selectable loop bandwidth (150 khz to 2 mhz) dual clock inputs w/manual or automatically controlled hitless switching dual clock outputs with selectable signal format (lvpecl, lvds, cml, cmos) support for itu g.709 and custom fec ratios (255/238, 255/237, 255/236) los, fos alarm outputs digitally-controlled ou tput phase adjust i 2 c or spi programmable on-chip voltage regulator for 1.8, 2.5, or 3.3 v 10% operation small size: 6 x 6 mm 36-lead qfn pb-free, rohs compliant p reliminary d ata s heet dspll ? ckout2 ckin1 ckout1 ckin2 n31 n2 nc1 nc2 signal detect device interrupt vdd (1.8, 2.5, or 3.3 v) gnd n32 clock select i 2 c/spi port control alarms
si5325 2 preliminary rev. 0.25 table 1. performance specifications (v dd = 1.8, 2.5, or 3.3 v 10%, t a = ?40 to 85 oc) parameter symbol test condition min typ max unit temperature range t a ?40 25 85 oc supply voltage v dd 2.97 3.3 3.63 v 2.25 2.5 2.75 v 1.62 1.8 1.98 v supply current i dd f out = 622.08 mhz both ckouts enabled lvpecl format output ? 251 279 ma ckout2 disabled ? 217 243 ma f out = 19.44 mhz both ckouts enabled cmos format output ? 204 234 ma ckout2 disabled ? 194 220 ma tristate/sleep mode ? tbd tbd ma input clock frequency (ckin1, ckin2) ck f input frequency and clock multiplication ratio deter- mined by programming device pll dividers. consult silicon laborato ries configu- ration software dspll sim at www.silabs.com/timing to determine pll divider set- tings for a given input fre- quency/clock multiplication ratio combination. 10 ? 710 mhz output clock frequency (ckout1, ckout2) ck of 10 970 1213 ? ? ? 945 1134 1417 mhz input clocks (ckin1, ckin2) differential voltage swing ckn dpp 0.25 ? 1.9 v pp common mode voltage ckn vcm 1.8 v 10% 0.9 ? 1.4 v 2.5 v 10% 1.0 ? 1.7 v 3.3 v 10% 1.1 ? 1.95 v rise/fall time ckn trf 20?80% ? 11 ns duty cycle ckn dc whichever is less 40 ? 60 % 50 ? ? ns output clocks (ckout1, ckout2) common mode v ocm lvpecl 100 ? load line-to-line v dd ?1.42 ? v dd ?1.25 v differential output swing v od 1.1 ? 1.9 v single ended output swing v se 0.5 ? 0.93 v note: for a more comprehensive listing of device specifications , please consult the silicon laboratories any-rate precision clock family reference manual. this document can be downloaded from www.silabs.com/timing .
si5325 preliminary rev. 0.25 3 rise/fall time cko trf 20?80% ? 230 350 ps duty cycle cko dc 45 ? 55 % pll performance jitter generation j gen f out = 622.08 mhz, lvpecl output format 50 khz?80 mhz ? 0.6 tbd ps rms 12 khz?20 mhz ? 0.6 tbd ps rms 800 hz?80 mhz ? tbd tbd ps rms jitter transfer j pk ?0.050.1db phase noise cko pn f out = 622.08 mhz 100 hz offset ? tbd tbd dbc/hz 1 khz offset ? tbd tbd dbc/hz 10 khz offset ? tbd tbd dbc/hz 100 khz offset ? tbd tbd dbc/hz 1 mhz offset ? tbd tbd dbc/hz subharmonic noise sp subh phase noise @ 100 khz off- set ? tbd tbd dbc spurious noise sp spur max spur @ n x f3 (n > 1, n x f3 < 100 mhz) ? tbd tbd dbc package thermal resistance junction to ambient ja still air ? 38 ? oc/w table 2. absolute maximum ratings parameter symbol value unit dc supply voltage v dd ?0.5 to 3.6 v lvcmos input voltage v dig ?0.3 to (v dd + 0.3) v operating junction temperature t jct ?55 to 150 c storage temperature range t stg ?55 to 150 c esd hbm tolerance (100 pf, 1.5 k ? )2kv esd mm tolerance 200 v latch-up tolerance jesd78 compliant note: permanent device damage may occur if the absolute maximu m ratings are exceeded. functional operation should be restricted to the conditions as specified in the operation se ctions of this data sheet. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. table 1. performance specifications (continued) (v dd = 1.8, 2.5, or 3.3 v 10%, t a = ?40 to 85 oc) parameter symbol test condition min typ max unit note: for a more comprehensive listing of device specifications , please consult the silicon laboratories any-rate precision clock family reference manual. this document can be downloaded from www.silabs.com/timing .
si5325 4 preliminary rev. 0.25 figure 1. typical phase noise plot 155.52 mhz in, 622.08 mhz out -160 -140 -120 -100 -80 -60 -40 -20 0 100 1000 10000 100000 1000000 10000000 100000000 offset frequency (hz) phase noise (dbc/hz )
si5325 preliminary rev. 0.25 5 figure 2. si5325 typical applicati on circuit (i2c control mode) figure 3. si5325 typical application circuit (spi control mode) si5325 int_c1b c2b rst ckout1+ ckout1? vdd gnd serial data serial clock reset interrupt/ckin_1 invalid indicator ckin_2 invalid indicator clock outputs ckout2+ ckout2? sda scl i 2 c interface serial port address a[2:0] cmode control mode (l) ckin1+ ckin1? input clock sources* ckin2+ ckin2? assumes differential lvpecl termination (3.3 v) on clock inputs. *note: ferrite bead system power supply c 3 c 2 c 1 c 4 0.1 f 0.1 f 0.1 f 1 f 0.1 f 100 ? 0.1 f + ? 0.1 f 100 ? 0.1 f + ? 130 ? 130 ? 82 ? 82 ? v dd = 3.3 v 130 ? 130 ? 82 ? 82 ? v dd = 3.3 v si5325 int_c1b c2b spi interface rst ckout1+ ckout1? vdd gnd reset interrupt/clkin_1 invalid indicator clkin_2 invalid indicator ckout2+ ckout2? serial data out serial data in sdo sdi serial clock sclk slave select ss cmode control mode (h) ckin1+ ckin1? input clock sources* ckin2+ ckin2? assumes differential lvpecl termination (3.3 v) on clock inputs. *note: clock outputs 0.1 f 100 ? 0.1 f + ? 0.1 f 100 ? 0.1 f + ? ferrite bead system power supply c 3 c 2 c 1 c 4 0.1 f 0.1 f 0.1 f 1 f 130 ? 130 ? 82 ? 82 ? v dd = 3.3 v 130 ? 130 ? 82 ? 82 ? v dd = 3.3 v
si5325 6 preliminary rev. 0.25 1. functional description the si5325 is a low jitter, precision clock multiplier for applications requiring clock multiplication without jitter attenuation. the si5325 accepts dual clock inputs ranging from 10 to 710 mhz and generates two independent, synchronous clock outputs ranging from 10 to 945 mhz and select frequencies to 1.4 ghz. the device provides virtually any frequency translation combination across this operating range. independent dividers are available for each input clock and output clock, so the si5325 can acc ept input clocks at different frequencies and it can ge nerate output clocks at different frequencies. the si5325 input clock frequency and clock multiplication ratio are programmable through an i 2 c or spi interface. silicon laboratories offers a pc-based software utility, dspll sim , that can be used to determine the optimum pll divider settings for a given input frequency/clo ck multiplication ratio combination that minimizes phase noise and power consumption. this utility can be downloaded from www.silabs.com/timing . the si5325 is based on s ilicon laboratories' 3rd- generation dspll ? technology, which provides any- rate frequency synthesis in a highly integrated pll solution that eliminates the need for external vcxo and loop filter components. the si5325 pll loop bandwidth is digitally programmable and supports a range from 30 khz to 1.3 mhz. the dspll sim software utility can be used to calculate valid loop bandwidth settings for a given input clock frequency/clock multiplication ratio. in the case when the input clocks enter alarm conditions, the pll will freeze the dco output frequency near its last val ue to maintain operation with an internal state close to the last valid operating state. the si5325 has two differential clock outputs. the electrical format of each clock output is independently programmable to support lvpecl, lvds, cml, or cmos loads. if not required, the second clock output can be powered down to minimize power consumption. the phase difference between the selected input clock and the output clocks is adjustable in 200 ps increments for system skew control. in addition, the phase of one output clock may be adjusted in relation to the phase of the other output clock. the resolution varies from 800 ps to 2.2 ns depending on the pll divider settings. consult the dspll sim configuration software to determine the phase offset resolution for a given input clock/clock multiplication ra tio combination. for system- level debugging, a bypass mode is available which drives the output clock dire ctly from the input clock, bypassing the internal dspll. the device is powered by a single 1.8, 2.5, or 3.3 v supply. 1.1. further documentation consult the silicon laborato ries any-rate precision clock family reference manual (frm) for more detailed information about the si5325. the frm can be downloaded from www.silabs.com/timing . silicon laboratories has developed a pc-based software utility called dspll sim to simplify device configuration, including frequency planning and loop bandwidth selection. this utility can be downloaded from www.silabs.com/timing .
si5325 preliminary rev. 0.25 7 2. pin descriptions: si5325 pin numbers are preliminary and subject to change. table 3. si5325 pin descriptions pin # pin name i/o signal level description 1 rst ilvcmos external reset. active low input that performs external hardware reset of device. resets all internal logi c to a known state and forces the device registers to their def ault value. clock outputs are tristated during reset. after rising edge of rst signal, the si5325 will perform an inte rnal self-calibration. this pin has a weak pull-up. 2, 7, 9, 11, 14, 15, 18, 19, 20, 30, 33 nc ? ? no connect. this pin must be left unc onnected for normal operation. 3 int_c1b o lvcmos interrupt/ckin1 invalid indicator. this pin functions as a device interrupt output or an alarm output for ckin1. if used as an interrupt output, int_pin must be set to 1. the pin functions as a maskable interrupt output with active polarity controlled by the int_pol register bit. if used as an alarm output, t he pin functions as a los (and optionally fos) alarm indicator for ckin1. set ck1_bad_pin = 1 and int_pin =0. 0 = ckin1 present. 1 = los (fos) on ckin1. the active polarity is controlled by ck_bad_pol . if no func- tion is selected, the pin tristates. note: internal register names are indicated by underlined italics, e.g. int_pin . see si5325 register map. 1 2 3 29 30 31 32 33 34 35 36 20 21 22 23 24 25 26 27 10 11 12 13 14 15 16 17 4 5 6 7 8 nc nc rst c2b int_c1b gnd vdd gnd vdd nc clkin2+ clkin2? nc nc clkin1+ clkin1? cs_ca scl sda_sdo a1 a2_ss sdi clkout1? nc gnd vdd nc clkout2? clkout2+ cmode gnd pad a0 nc 9 18 19 28 nc nc nc clkout1+
si5325 8 preliminary rev. 0.25 4c2bolvcmos ckin2 invalid indicator. this pin functions as a los (and optionally fos) alarm indi- cator for ckin2 if ck2_bad_pin =1. 0 = ckin2 present. 1 = los (fos) on ckin2. the active polarity can be changed by ck_bad_pol . if ck2_bad_pin = 0, the pin tristates. 5, 10, 32 v dd v dd supply supply. the device operates from a 1.8, 2.5, or 3.3 v supply. bypass capacitors should be associated with the following vdd pins: 5 0.1 f 10 0.1 f 32 0.1 f a 1.0 f should be placed as close to device as is practical. 6, 8, 31 gnd gnd supply ground. must be connected to system ground. minimize the ground path impedance for optimal performance of this device. 12 13 ckin2+ ckin2? imulti clock input 2. differential input clock. this input can also be driven with a single-ended signal. input frequency range is 10 to 710 mhz. 16 17 ckin1+ ckin1? imulti clock input 1. differential input clock. this input can also be driven with a single-ended signal. input frequency range is 10 to 710 mhz. 21 cs_ca i/o lvcmos input clock select/active clock indicator. in manual clock selection mode, this pin functions as the manual input clock selector if the cksel_pin is set to 1. 0 = select ckin1. 1 = select ckin2. if cksel_pin =0, the cksel_reg register bit controls this function and this input tristates. in automatic clock selection mode , this pin indicates which of the two input clocks is currently the active clock. if alarms exist on both clocks, ca will indi cate the last active clock that was used before entering the digital hold state. the ck_actv_pin register bit must be set to 1 to reflect the active clock status to the ca output pin. 0 = ckin1 active input clock. 1 = ckin2 active input clock. if ck_actv_pin = 0, this pin will tristate. the ca status will always be reflected in the ck_actv_reg read only register bit. 22 scl i lvcmos serial clock/ serial clock. this pin functions as the serial clock input for both spi and i 2 c modes. table 3. si5325 pin descriptions (continued) pin # pin name i/o signal level description note: internal register names are indicated by underlined italics, e.g. int_pin . see si5325 register map.
si5325 preliminary rev. 0.25 9 23 sda_sdo i/o lvcmos serial data. in i 2 c control mode (cmode = 0), this pin functions as the bidirectional serial data port. in spi control mode (cmode = 1), this pin functions as the serial data output. 25 24 a1 a0 ilvcmos serial port address. in i 2 c control mode (cmode = 0), these pins function as hardware controlled address bits. in spi control mode (cmode = 1), these pins are ignored. 26 a2_s s ilvcmos serial port address/slave select. in i 2 c control mode (cmode = 0), this pin functions as a hardware controlled address bit. in spi control mode (cmode = 1), this pin functions as the slave select input. 27 sdi i lvcmos serial data in. in i 2 c control mode (cmode = 0), this pin is ignored. in spi control mode (cmode = 1), this pin functions as the serial data input. 29 28 ckout1? ckout1+ omulti output clock 1. differential output clock with a frequency range of 10 mhz to 1.4175 ghz. output signal format is selected by sfout1_reg register bits. output is differential for lvpecl, lvds, and cml compatible modes. for cmos for- mat, both output pins drive identical single-ended clock out- puts. 34 35 ckout2? ckout2+ omulti output clock 2. differential output clock with a frequency range of 10 mhz to 1.4175 ghz. output signal format is selected by sfout2_reg register bits. output is differential for lvpecl, lvds, and cml compatible modes. for cmos for- mat, both output pins drive identical single-ended clock out- puts. 36 cmode i lvcmos control mode. selects i 2 c or spi control mode for the si5325. 0 = i 2 c control mode. 1 = spi control mode. gnd pad gnd gnd supply ground pad. the ground pad must provide a low thermal and electrical impedance to a ground plane. table 3. si5325 pin descriptions (continued) pin # pin name i/o signal level description note: internal register names are indicated by underlined italics, e.g. int_pin . see si5325 register map.
si5325 10 preliminary rev. 0.25 3. ordering guide ordering part number output clock frequency range package temperature range si5325a-b-gm 10?945 mhz 970?1134 mhz 1.213?1.417 ghz 36-lead 6 x 6 mm qfn ?40 to 85 c si5325b-b-gm 10?808 mhz 36-lead 6 x 6 mm qfn ?40 to 85 c si5325c-b-gm 10?346 mhz 36-lead 6 x 6 mm qfn ?40 to 85 c
si5325 preliminary rev. 0.25 11 4. package outline: 36-pin qfn figure 4 illustrates the package details for the si5325. table 4 lis ts the values for the di mensions shown in the illustration. figure 4. 36-pin quad flat no-lead (qfn) table 4. package dimensions symbol millimeters symbol millimeters min nom max min nom max a 0.80 0.85 0.90 l 0.50 0.60 0.75 a1 0.00 0.01 0.05 ??12o b 0.18 0.23 0.30 aaa ? ? 0.10 d 6.00 bsc bbb ? ? 0.10 d2 3.95 4.10 4.25 ccc ? ? 0.05 e 0.50 bsc ddd ? ? 0.10 e 6.00 bsc eee ? ? 0.05 e2 3.95 4.10 4.25 notes: 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jede c outline mo-220, variation vjjd. 4. recommended card reflow profile is per the jede c/ipc j-std-020c specif ication for small body components.
si5325 12 preliminary rev. 0.25 5. recommended pcb layout figure 5. pcb land pattern diagram
si5325 preliminary rev. 0.25 13 table 5. pcb land pattern dimensions dimension min max e 0.50 bsc. e5.42 ref. d5.42 ref. e2 4.00 4.20 d2 4.00 4.20 ge 4.53 ? gd 4.53 ? x ? 0.28 y0.89 ref. ze ? 6.31 zd ? 6.31 notes (general): 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per the ansi y14.5m-1994 specification. 3. this land pattern design is based on ipc-sm-782 guidelines. 4. all dimensions shown are at maximum ma terial condition (mmc ). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. notes (solder mask design): 1. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. notes (stenc il design): 1. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 4. a 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center ground pad. notes (card assembly): 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per the jedec/ipc j-std-020c specification for small body components.
si5325 14 preliminary rev. 0.25 d ocument c hange l ist revision 0.23 to revision 0.24 clarified that the two outputs have a common, higher frequency source on page 1. changed lvttl to lvcmos in table 2, ?absolute maximum ratings,? on page 3. added figure 1, ?typical phase noise plot,? on page 4. updated ?2. pin descriptions: si5325?. removed references to late ncy control, inc, and dec. changed font for register names to underlined italics. updated "3. ordering guide" on page 10. added ?5. recommended pcb layout?. revision 0.24 to revision 0.25 updated section "2. pin descriptions: si5325" on page 7.
si5325 preliminary rev. 0.25 15 n otes :
si5325 16 preliminary rev. 0.25 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: clockinfo@silabs.com internet: www.silabs.com silicon laboratories, silicon labs, and dspll are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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